{"id":323,"date":"2021-04-15T14:29:50","date_gmt":"2021-04-15T14:29:50","guid":{"rendered":"http:\/\/dataninja.nrw\/?page_id=323"},"modified":"2025-02-10T08:42:00","modified_gmt":"2025-02-10T08:42:00","slug":"nirehaps-neuro-inspired-and-resource-efficient-hardware-architectures-for-plastic-snns","status":"publish","type":"page","link":"https:\/\/dataninja.nrw\/?page_id=323","title":{"rendered":"NireHApS: Neuro-inspired and resource-efficient Hardware-Architectures for plastic SNNs"},"content":{"rendered":"\n<h3 class=\"wp-block-heading\">Goal<\/h3>\n\n\n\n<p>Many application areas require resource-efficient computations, for example, computer vision tasks in production. Artificial Intelligence solutions that allow to adapt online to changing conditions in such tasks are promising, but often involve large models and costly computations. This project aims at exploring in how far biological-inspired spiking neural network architectures can be employed in hardware which, on the one hand, allows for efficient computation, and, on the other hand, facilitates online adaption and learning.<\/p>\n\n\n\n<figure class=\"wp-block-image size-large is-style-default\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"724\" src=\"https:\/\/dataninja.nrw\/wp-content\/uploads\/2022\/05\/07_NireHApS_A3_vs1-scaled-1-1024x724.jpg\" alt=\"\" class=\"wp-image-841\" srcset=\"https:\/\/dataninja.nrw\/wp-content\/uploads\/2022\/05\/07_NireHApS_A3_vs1-scaled-1-1024x724.jpg 1024w, https:\/\/dataninja.nrw\/wp-content\/uploads\/2022\/05\/07_NireHApS_A3_vs1-scaled-1-300x212.jpg 300w, https:\/\/dataninja.nrw\/wp-content\/uploads\/2022\/05\/07_NireHApS_A3_vs1-scaled-1-768x543.jpg 768w, https:\/\/dataninja.nrw\/wp-content\/uploads\/2022\/05\/07_NireHApS_A3_vs1-scaled-1-1536x1086.jpg 1536w, https:\/\/dataninja.nrw\/wp-content\/uploads\/2022\/05\/07_NireHApS_A3_vs1-scaled-1-2048x1448.jpg 2048w\" sizes=\"(max-width: 1024px) 100vw, 1024px\" \/><figcaption class=\"wp-element-caption\"><em>Illustration: Christoph J Kellner, Studio Animanova<\/em><\/figcaption><\/figure>\n\n\n\n<h3 class=\"wp-block-heading\">Project Overview<\/h3>\n\n\n\n<p>Implementing online learning methods into resource efficient hardware will allow to embed such methods directly on sensor hardware, reducing high-bandwidth communications and allow for faster processing. The project will use current embedded (and many core) hardware architectures for testing online learning methods directly in hardware and applied in spiking neural networks. As one example, these systems will be employed for ultra-high-speed computer vision and event detection.<\/p>\n\n\n\n<figure class=\"wp-block-image size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"340\" src=\"https:\/\/dataninja.nrw\/wp-content\/uploads\/2021\/04\/illustration-2-1024x340.png\" alt=\"\" class=\"wp-image-460\" style=\"width:629px;height:209px\" srcset=\"https:\/\/dataninja.nrw\/wp-content\/uploads\/2021\/04\/illustration-2-1024x340.png 1024w, https:\/\/dataninja.nrw\/wp-content\/uploads\/2021\/04\/illustration-2-300x100.png 300w, https:\/\/dataninja.nrw\/wp-content\/uploads\/2021\/04\/illustration-2-768x255.png 768w, https:\/\/dataninja.nrw\/wp-content\/uploads\/2021\/04\/illustration-2.png 1420w\" sizes=\"(max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n\n\n\n<p>The project will explore the design-space of possible embedded hardware architectures and analyze resource-efficient implementations of biologically-inspired spiking neural networks. The different architectures will be applied in Artificial Intelligence tasks as, for example, in online learning in computer vision. First, with respect to hardware architectures this will cover reconfigurable hardware platforms as FPGA and application specific many-core systems. Secondly, different neuron and synapse models \u2013 as well as configurations of these model \u2013 will be evaluated, for example variations of spike-timing dependent plasticity. The hardware platforms will finally be coupled with event-based sensors (e.g. DVS cameras) to evaluate the solutions on the basis of practical application scenarios.<\/p>\n\n\n\n<p><span data-has-children=\"true\" id=\"2af382dc-6f13-420d-a3fe-ed94f3524f9a\" data-items=\"[&quot;3636714888&quot;,&quot;2884531079&quot;,&quot;1893721212&quot;,&quot;3943502580&quot;]\" class=\"abt-citation\" contenteditable=\"false\"><sup>\u200b1\u20134\u200b<\/sup><\/span><\/p>\n\n\n\n<p>Target platforms are FPGAs and multi-core processor architectures. UBI uses high-level synthesis (HLS) and parameterizable VHDL and Verilog code for mapping on FPGAs. For online learning, the weights of neurons and synapses can be adjusted during runtime, or changes to the network structure can be achieved by replacing the bitstream (reconfiguration or (partial) dynamic reconfiguration). Utilizing the synaptic delay enables larger networks to be mapped without restricting the maximum clock frequency. The specified synapse delay between distant neurons can be implemented by memory elements (several clock cycles). The event-driven processing supports hierarchical clock gating, and sensible network segmentation (grouping of groups of neurons that are often firing simultaneously in clock regions) offers potential for optimizing energy efficiency.<\/p>\n\n\n\n<p>The FHBI examines the suitability of the multi-core and RISC-V-based architectures as specialized processor architectures. For these, the integration of special hardware extensions (e.g., instruction set extensions, VLIW, vector extension) is examined. Many-core architectures are typically based on a hierarchical communication infrastructure with shared resources (e.g., shared bus, shared memory) and a global network-on-chip (NoC). The analysis of the hardware implementation of the SNN provides information about which operations (properties of the neuron model, complexity of the learning rules) have a significant influence on resource efficiency. The application of the above-mentioned learning strategies for online adaptation is examined for both target architectures. Also, the target architectures will be coupled with event-based sensors for evaluating the solutions of ultra-high-speed computer vision and event detection tasks.<\/p>\n\n\n\n<hr class=\"wp-block-separator has-css-opacity is-style-wide\"\/>\n\n\n\n<h3 class=\"wp-block-heading\">Preliminary Results:<\/h3>\n\n\n\n<p>As for the first assessment, we have done the literature research on spiking neural networks and simulated the SNNs using the brian2 simulator to understand the behavior of the neurons and neuronal models. For getting hands-on with practical applications, we realized a Binary Neuronal Associative Memory (BiNAM) using SNNs [1]. We investigated how the storage efficiency behaves with varying samples and other essential model parameters like threshold and weights. The critical model parameters are determined by performing multiple experiments.<\/p>\n\n\n\n<p>On the other hand, to perform in silico analysis, in order to gain accurate parametric values and observe the complete behavior of an SNN model, a different set of input conditions, i.e., what values are required, which component values are dependent on each other, must be defined in each event. Even though the group of neurons is moderate-sized, the combinations of these component inputs into the model may require very precious values to be defined and simulated. However, a significant amount of dedicated simulators have been developed to analyze and visualize the SNNs behavior. Such simulators are providing the users to acquire precise simulations in a relatively short period of time. Nevertheless, there are many challenges and computational issues related to SNN. In some cases, it requires the use of accurate biological representations of the neurons. Alternately, a real-time capability with the model provides a more appropriate way to make direct changes at any instant of time in the simulation to observe the model behavior.<br>With this motivation behind and the existing challenges in understanding and leveraging the promising features of SNNs, we present the first version of our novel spiking neural network user-friendly software tool named RAVSim (Run-time Analysis and Visualization Simulator), which provides a runtime environment to analyze and simulate the SNNs model [2]. It is an interactive and intuitive tool designed to help in knowing considerable parameters involved in the working of the neurons, their dependency on each other, determining the essential parametric values, and the communication between the neurons for replicating the way the human brain works. Moreover, the proposed SNNs model analysis and simulation algorithm used in RAVSim takes significantly less time in order to estimate and visualize the behavior of the parametric values during a runtime environment.<\/p>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"380\" src=\"https:\/\/dataninja.nrw\/wp-content\/uploads\/2022\/07\/sim-1024x380.jpg\" alt=\"\" class=\"wp-image-892\" srcset=\"https:\/\/dataninja.nrw\/wp-content\/uploads\/2022\/07\/sim-1024x380.jpg 1024w, https:\/\/dataninja.nrw\/wp-content\/uploads\/2022\/07\/sim-300x111.jpg 300w, https:\/\/dataninja.nrw\/wp-content\/uploads\/2022\/07\/sim-768x285.jpg 768w, https:\/\/dataninja.nrw\/wp-content\/uploads\/2022\/07\/sim-1536x571.jpg 1536w, https:\/\/dataninja.nrw\/wp-content\/uploads\/2022\/07\/sim.jpg 1962w\" sizes=\"(max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n\n\n\n<p><\/p>\n\n\n\n<p><span style=\"text-decoration: underline;\">RAVSim Availability:<\/span><br>The RAVSim (v1.0) is an open-source simulator<\/p>\n\n\n\n<ul>\n<li>it is published on LabVIEW\u2019s official website and available publicly at<br><a href=\"https:\/\/www.ni.com\/de-de\/support\/downloads\/tools-network\/download.run-time-analysis-and-visualization-simulator--ravsim-.html#443936\">https:\/\/www.ni.com\/de-de\/support\/downloads\/tools-network\/download.run-time-analysis-and-visualization-simulator&#8211;ravsim-.html#443936<\/a><\/li>\n\n\n\n<li>video demonstration can be accessed on our Youtube channel: <a href=\"https:\/\/www.youtube.com\/watch?v=Ozv0MXXj89Y\">https:\/\/www.youtube.com\/watch?v=Ozv0MXXj89Y<\/a><\/li>\n\n\n\n<li>user manual is available on our GitHub Repository: <a href=\"https:\/\/github.com\/Rao-Sanaullah\/RAVSim\/tree\/main\/User-Manual\">https:\/\/github.com\/Rao-Sanaullah\/RAVSim\/tree\/main\/User-Manual<\/a><\/li>\n<\/ul>\n\n\n\n<hr class=\"wp-block-separator has-css-opacity is-style-wide\"\/>\n\n\n\n<h3 class=\"wp-block-heading\">References<\/h3>\n\n\n\n<section aria-label=\"References\" class=\"wp-block-abt-static-bibliography abt-static-bib\" role=\"region\"><ol class=\"abt-bibliography__body\"><\/ol><\/section>\n\n\n\n<section aria-label=\"Bibliography\" class=\"wp-block-abt-bibliography abt-bibliography\" role=\"region\"><ol class=\"abt-bibliography__body\" data-entryspacing=\"1\" data-maxoffset=\"3\" data-linespacing=\"1\" data-second-field-align=\"flush\"><li id=\"3636714888\">  <div class=\"csl-entry\">\n    <div class=\"csl-left-margin\">1. <\/div><div class=\"csl-right-inline\">S. Lutkemeier, T. Jungeblut, H. K. O. Berge, S. Aunet, M. Porrmann, U. Ruckert. A 65 nm 32 b Subthreshold Processor With 9T Multi-Vt SRAM and Adaptive Supply Voltage Control. <i>IEEE Journal of Solid-State Circuits<\/i>. 2013;48:8-19. doi:<a href=\"https:\/\/doi.org\/10.1109\/JSSC.2012.2220671\">10.1109\/JSSC.2012.2220671<\/a><\/div>\n  <\/div>\n<\/li><li id=\"2884531079\">  <div class=\"csl-entry\">\n    <div class=\"csl-left-margin\">2. <\/div><div class=\"csl-right-inline\">Ostrau C, Klarhorst C, Thies M, R\u00fcckert U. Benchmarking and Characterization of event-based Neuromorphic Hardware. In: ; 2019. <a href=\"https:\/\/pub.uni-bielefeld.de\/record\/2935328\">https:\/\/pub.uni-bielefeld.de\/record\/2935328<\/a><\/div>\n  <\/div>\n<\/li><li id=\"1893721212\">  <div class=\"csl-entry\">\n    <div class=\"csl-left-margin\">3. <\/div><div class=\"csl-right-inline\">J. Ax, N. Kucza, M. Vohrmann, T. Jungeblut, M. Porrmann, U. R\u00fcckert. Comparing Synchronous, Mesochronous and Asynchronous NoCs for GALS Based MPSoCs. In: <i>2017 IEEE 11th International Symposium on Embedded Multicore\/Many-Core Systems-on-Chip (MCSoC)<\/i>. ; 2017:45-51. doi:<a href=\"https:\/\/doi.org\/10.1109\/MCSoC.2017.19\">10.1109\/MCSoC.2017.19<\/a><\/div>\n  <\/div>\n<\/li><li id=\"3943502580\">  <div class=\"csl-entry\">\n    <div class=\"csl-left-margin\">4. <\/div><div class=\"csl-right-inline\">J. Ax, G. Sievers, J. Daberkow, et al. CoreVA-MPSoC: A Many-Core Architecture with Tightly Coupled Shared and Local Data Memories. <i>IEEE Transactions on Parallel and Distributed Systems<\/i>. 2018;29:1030-1043. doi:<a href=\"https:\/\/doi.org\/10.1109\/TPDS.2017.2785799\">10.1109\/TPDS.2017.2785799<\/a><\/div>\n  <\/div>\n<\/li><\/ol><\/section>\n\n\n\n<h3 class=\"wp-block-heading\">Cooperation<\/h3>\n\n\n\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-layout-1 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:100%\">\n<div class=\"wp-block-columns\">\n    <div class=\"wp-block-column contrib-container\" style=\"flex-basis:20%\">\n        <a href=\"https:\/\/www.fh-bielefeld.de\/en\"><img decoding=\"async\" loading=\"lazy\" src=\"https:\/\/dataninja.nrw\/wp-content\/uploads\/2023\/12\/HSBI_Logo_RGB_schwarz.svg_.png\" alt=\"\" class=\"wp-image-197\" height=\"100%\"><\/a>\n    <\/div>\n    <div class=\"wp-block-column\" style=\"margin-right:0.5cm\"><\/div>\n    <div class=\"wp-block-column\" style=\"flex-basis:80%\">\n        <a href=\"https:\/\/www.hsbi.de\/en\"><b><p class=\"contrib-card-label\">Industrial Internet of Things Group<\/p><\/b><\/a>\n        <a href=\"https:\/\/www.hsbi.de\/personenverzeichnis\/thorsten-jungeblut\"><p class=\"contrib-card-label\">Prof. Dr.-Ing. habil. Thorsten Jungeblut<\/p><\/a>\n        <p class=\"contrib-card-label\">PhD student: <a href=\"https:\/\/www.hsbi.de\/personenverzeichnis\/sanaullah\">Sanaullah<\/a><\/p>\n    <\/div>\n<\/div>\n<div class=\"wp-block-columns\">\n    <div class=\"wp-block-column contrib-container\" style=\"flex-basis:20%;\">\n        <a href=\"https:\/\/uni-bielefeld.de\/\"><img decoding=\"async\" width=\"459\" height=\"110\" loading=\"lazy\" src=\"https:\/\/dataninja.nrw\/wp-content\/uploads\/2021\/04\/uni_bi_logo-3.png\" alt=\"\" class=\"wp-image-197\" srcset=\"https:\/\/dataninja.nrw\/wp-content\/uploads\/2021\/04\/uni_bi_logo-3.png 459w, https:\/\/dataninja.nrw\/wp-content\/uploads\/2021\/04\/uni_bi_logo-3-300x72.png 300w\" sizes=\"(max-width: 459px) 100vw, 459px\" \/><\/a>\n    <\/div>\n    <div class=\"wp-block-column\" style=\"margin-right:0.5cm\"><\/div>\n    <div class=\"wp-block-column\" style=\"flex-basis:80%\">\n        <a href=\"https:\/\/www.cit-ec.de\/en\/ks\"><b><p class=\"contrib-card-label\">Cognitronics and Sensor Systems Group<\/p><\/b><\/a>\n        <a href=\"https:\/\/www.cit-ec.de\/en\/ks\/staff\/prof-dr-ing-ulrich-ruckert\"><p class=\"contrib-card-label\">Prof. Dr.-Ing. Ulrich R\u00fcckert<\/p><\/a>\n        <p class=\"contrib-card-label\">PhD student: <a href=\"https:\/\/ekvv.uni-bielefeld.de\/pers_publ\/publ\/PersonDetail.jsp?personId=289915027\">Shamini Koravuna<\/a><\/p>\n    <\/div>\n<\/div>\n<\/div>\n<\/div>\n\n\n\n<hr class=\"wp-block-separator has-css-opacity is-style-wide\"\/>\n\n\n\n<h3 class=\"wp-block-heading\">Project Publications<\/h3>\n\n\n\n<ul>\n<li>Attaullah, Hasina, Sanaullah, and Thorsten Jungeblut (2024a). \u2018\u2018Analyzing Machine Learning Models for Activity Recognition Using Homomorphically Encrypted Real-World Smart Home Datasets: A Case Study\u2019\u2019. In:\u00a0Applied Sciences\u00a014.19, p. 9047.<\/li>\n\n\n\n<li>Attaullah, Hasina, Sanaullah, and Thorsten Jungeblut (2024b). \u2018\u2018FL-DL: Fuzzy Logic with Deep Learning, Hybrid Anomaly Detection and Activity Prediction in Smart Homes Data-Sets.\u2019\u2019 In:\u00a0In International Conference and Symposium on Computational Intelligence and Informatics (CINTI).<\/li>\n\n\n\n<li>Koravuna, Shamini, Sanaullah, Thorsten Jungeblut, and Ulrich R\u00fcckert (2023). \u2018\u2018Digit Recognition Using Spiking Neural Networks on FPGAs\u2019\u2019. In:International Work-Conference on Artificial Neural Networks (IWANN) Conference. Springer International Publishing, pp. 406\u2013417.<\/li>\n\n\n\n<li>Koravuna, Shamini, Sanaullah, Thorsten Jungeblut, and Ulrich R\u00fcckert (2024). \u2018\u2018Spiking Neural Network Models Analysis on Field Programmable Gate Arrays\u2019\u2019. In:\u00a02024 International Conference on Intelligent and Innovative Computing Applications (ICONIC) &#8211; 4th Edition, pp. 259\u2013270.<\/li>\n\n\n\n<li>Pennino, Federico, Shamini Koravuna, Christoph Ostrau, and Ulrich R\u00fcckert (2022). \u2018\u2018N-MNIST object recognition with Spiking Neural Networks\u2019\u2019. In: Dataninja Spring School, Poster Presentation.<\/li>\n\n\n\n<li>Sanaullah, Amanullah, Kaushik Roy, Jeong-A Lee, Son Chul-Jun, and Thorsten Jungeblut (2023). \u2018\u2018A Hybrid Spiking-Convolutional Neural Network Approach for Advancing High-Quality Image Inpainting\u2019\u2019. In:\u00a0IEEE Conference on Computer Vision (ICCV) at Workshop PerDream.<\/li>\n\n\n\n<li>Sanaullah, Hasina Attaullah, and Thorsten Jungeblut (2024a). \u2018\u2018Encryption Techniques for Privacy-Preserving CNN Models: Performance and Practicality in Urban AI Applications\u2019\u2019. In:\u00a0Proceedings of the 2nd ACM SIGSPATIAL International Workshop on Advances in Urban-AI. UrbanAI\u201924. Atlanta, GA, USA: Association for Computing Machinery, pp. 50\u201353.\u00a0isbn: 9798400711565.\u00a0doi:\u00a010.1145\/3681780.3697244.\u00a0url:https:\/\/doi.org\/10.1145\/3681780.3697244.<\/li>\n\n\n\n<li>Sanaullah, Hasina Attaullah, and Thorsten Jungeblut (2024b). \u2018\u2018The Next-Gen Interactive Runtime Simulator for Neural Network Programming\u2019\u2019. In: Companion Proceedings of the 8th International Conference on the Art, Science, and Engineering of Programming, pp. 8\u201310.<\/li>\n\n\n\n<li>Sanaullah, Hasina Attaullah, and Thorsten Jungeblut (2024c). \u2018\u2018Trade-offs between privacy and performance in encrypted dataset using machine learning models\u2019\u2019. In:\u00a0DataNinja sAIOnARA Conference, pp. 39\u201342. doi: <a href=\"https:\/\/doi.org\/10.11576\/dataninja-1166\">https:\/\/doi.org\/10.11576\/dataninja-1166<\/a>.<\/li>\n\n\n\n<li>Sanaullah and Thorsten Jungeblut (2023). \u2018\u2018&#8221;Analysis of MR Images for Early and Accurate Detection of Brain Tumor Using Resource Efficient Simulator Brain Analysis&#8221;\u2019\u2019. In:\u00a0International Conference on Machine Learning and Data Mining (MLDM) Conference.<\/li>\n\n\n\n<li>Sanaullah, Shamini Koravuna, Ulrich R\u00fcckert, and Thorsten Jungeblut (2022a). \u2018\u2018Real-time resource efficient simulator for snns-based model experimentation\u2019\u2019. In:\u00a0Dataninja Spring School, Poster Presentation. <\/li>\n\n\n\n<li>Sanaullah, Shamini Koravuna, Ulrich R\u00fcckert, and Thorsten Jungeblut (2022b). \u2018\u2018SNNs Model Analyzing and Visualizing Experimentation Using RAVSim\u2019\u2019. In:\u00a0Engineering Applications of Neural Networks (EANN). Vol. 161. Springer, pp. 40\u201351.<\/li>\n\n\n\n<li>Sanaullah, Shamini Koravuna, Ulrich R\u00fcckert, and Thorsten Jungeblut (2023a). \u2018\u2018A Novel Spike Vision Approach for Robust Multi-Object Detection Using SNNs\u2019\u2019. In:\u00a0Novel Trends in Data Science (NTDS) Conference.<\/li>\n\n\n\n<li>Sanaullah, Shamini Koravuna, Ulrich R\u00fcckert, and Thorsten Jungeblut (2023b). \u2018\u2018Design-Space Exploration of SNN Models using Application-Specific Multi-Core Architectures\u2019\u2019. In:\u00a0Neuro-Inspired Computing Elements (NICE) Conference.<\/li>\n\n\n\n<li>Sanaullah, Shamini Koravuna, Ulrich R\u00fcckert, and Thorsten Jungeblut (2023c). \u2018\u2018Evaluating Spiking Neural Network Models: A Comparative Performance Analysis\u2019\u2019. In:\u00a0Dataninja Spring School Poster Presentation.<\/li>\n\n\n\n<li>Sanaullah, Shamini Koravuna, Ulrich R\u00fcckert, and Thorsten Jungeblut (2023d). \u2018\u2018Evaluation of Spiking Neural Nets-Based Image Classification Using the Runtime Simulator RAVSim\u2019\u2019. In:\u00a0International Journal of Neural Systems, pp. 2350044\u20132350044.<\/li>\n\n\n\n<li>Sanaullah, Shamini Koravuna, Ulrich R\u00fcckert, and Thorsten Jungeblut (2023e). \u2018\u2018Exploring spiking neural networks: a comprehensive analysis of mathematical models and applications\u2019\u2019. In:\u00a0Frontiers in Computational Neuroscience. Vol. 17. Frontiers Media SA.<\/li>\n\n\n\n<li>Sanaullah, Shamini Koravuna, Ulrich R\u00fcckert, and Thorsten Jungeblut (2023f). \u2018\u2018Streamlined Training of GCN for Node Classification with Automatic Loss Function and Optimizer Selection\u2019\u2019. In:\u00a0Engineering Applications of Neural Networks (EANN). Springer International Publishing, pp. 191\u2013202.<\/li>\n\n\n\n<li>Sanaullah, Shamini Koravuna, Ulrich R\u00fcckert, and Thorsten Jungeblut (2023g). \u2018\u2018Transforming event-based into spike-rate datasets for enhancing neuronal behavior simulation to bridging the gap for snns\u2019\u2019. In:\u00a0IEEE Conference on Computer Vision (ICCV) at Workshop PerDream.<\/li>\n\n\n\n<li>Sanaullah, Shamini Koravuna, Ulrich R\u00fcckert, and Thorsten Jungeblut (2024a). \u2018\u2018A Spike Vision Approach for Multi-object Detection and Generating Dataset Using Multi-core Architecture on Edge Device\u2019\u2019. In:\u00a0Engineering Applications of Neural Networks (EANN). Springer International Publishing, pp. 317\u2013328.<\/li>\n\n\n\n<li>Sanaullah, Shamini Koravuna, Ulrich R\u00fcckert, and Thorsten Jungeblut (2024b). \u2018\u2018Advancements in Neural Network Generations\u2019\u2019. In:\u00a0DataNinja sAIOnARA 2024 Conference, pp. 43\u201346.\u00a0doi: <a href=\"https:\/\/doi.org\/10.11576\/dataninja-1167.\">https:\/\/doi.org\/10.11576\/dataninja-1167.<\/a><\/li>\n\n\n\n<li>Sanaullah, Kaushik Roy, Ulrich R\u00fcckert, and Thorsten Jungeblut (2024a). \u2018\u2018A Hybrid Spiking-Convolutional Neural Network Approach for Advancing Machine Learning Models\u2019\u2019. In:\u00a0Northern Lights Deep Learning Conference. PMLR, pp. 220\u2013227.<\/li>\n\n\n\n<li>Sanaullah, Kaushik Roy, Ulrich R\u00fcckert, and Thorsten Jungeblut (2024b). \u2018\u2018Poster: Selection of Optimal Neural Model using Spiking Neural Network for Edge Computing\u2019\u2019. In:\u00a02024 IEEE 44th International Conference on Distributed Computing Systems (ICDCS). IEEE, pp. 1452\u20131453.<\/li>\n<\/ul>\n\n\n\n<hr class=\"wp-block-separator has-css-opacity is-style-wide\"\/>\n","protected":false},"excerpt":{"rendered":"<p>Goal Many application areas require resource-efficient computations, for example, computer vision tasks in production. Artificial Intelligence solutions that allow to [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":841,"parent":119,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"ub_ctt_via":"","footnotes":""},"featured_image_src":"https:\/\/dataninja.nrw\/wp-content\/uploads\/2022\/05\/07_NireHApS_A3_vs1-scaled-1.jpg","_links":{"self":[{"href":"https:\/\/dataninja.nrw\/index.php?rest_route=\/wp\/v2\/pages\/323"}],"collection":[{"href":"https:\/\/dataninja.nrw\/index.php?rest_route=\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/dataninja.nrw\/index.php?rest_route=\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/dataninja.nrw\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/dataninja.nrw\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=323"}],"version-history":[{"count":15,"href":"https:\/\/dataninja.nrw\/index.php?rest_route=\/wp\/v2\/pages\/323\/revisions"}],"predecessor-version":[{"id":2723,"href":"https:\/\/dataninja.nrw\/index.php?rest_route=\/wp\/v2\/pages\/323\/revisions\/2723"}],"up":[{"embeddable":true,"href":"https:\/\/dataninja.nrw\/index.php?rest_route=\/wp\/v2\/pages\/119"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/dataninja.nrw\/index.php?rest_route=\/wp\/v2\/media\/841"}],"wp:attachment":[{"href":"https:\/\/dataninja.nrw\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=323"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}